1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, it is suitable for use in a semiconductor memory device in which a same pad is shared for an address input and data input/output.
2. Description of the Related Art
In a memory in recent years, there is the one in which a same pad is used to perform an input/output of an address and data to reduce the number of pads. In such memory, it is controlled such that the input of the address and the output of the data do not occur simultaneously in a read operation of data. Operational waveforms chart in a conventional data read operation is shown in FIG. 7.
At first, after a chip enable signal /CE changes from high level (hereinafter, referred to as “H”) to low level (hereinafter, referred to as “L”) at the time T11, an address valid signal (address capture signal)/ADV changes from “H” to “L” at the time T12. A memory captures an external address (ADDRESS) inside thereof, inputted from a shared pad of the address/data (ADQ) during a period when the address valid signal /ADV is “L” (times T12 to T13).
Subsequently, after the address valid signal /ADV turns to “H” at the time T13, an output enable signal /OE changes from “H” to “L” at the time T14, and thereby, the memory starts and performs an internal read operation. The memory outputs the data (DATA) read by the internal read operation to external from the shared pad of the address/data (ADQ) at the time T15 when a predetermined time elapses from the time T14 when the memory starts the internal read operation.
As stated above, the internal read operation is inhibited during the period when the address valid signal /ADV is “L”, so that the input of the external address and the output of the read data do not occur simultaneously. A high impedance (Hi-Z) state of the output in the memory is released at the time when the internal read operation is started when both signals /CE, /OE are “L”, to be a low impedance (Low-Z) state.
Besides, a semiconductor memory device, in which an input/output of address and data are performed by using a same pad, and an output is turned to a Hi-Z state at the time of writing of address from external, is described in Patent Document 1.    [Patent Document 1] Japanese Patent Application Laid-open No. Sho 55-89985
As stated above, in the memory performing the input/output of address and data by using the same pad, the Hi-Z state of the output is generally released to be the Low-Z state at time when the memory starts the internal read operation (both signals /CE, /OE are “L”). Besides, the external address is captured inside from the time when the address valid signal /ADV falls from “H” to “L”, and therefore, it is not necessary to wait the start of the internal read operation until the address valid signal /ADV turns to “H” again from the point of view of an internal operation. It is preferable to start the internal read operation in early time to realize a high-speed operation.
However, when the memory starts the internal read operation before the address valid signal /ADV turns to “H” again, a bus fight occurs as shown in FIG. 8, and therefore, it is impossible to turn the output in the memory to the Low-Z state when the external address is inputted from a controller side.
FIG. 8 is a view showing operational waveforms when it is assumed that the memory starts the internal read operation before the address valid signal /ADV turns to “H” again.
At first, after the chip enable signal /CE turns to “L” at the time T21, the address valid signal /ADV turns to “L” at the time T22, and the memory captures the external address (ADDRESS) inputted from the shared pad of address/data (ADQ) into inside thereof. The external address is supplied to the memory from the controller side during the period when the address valid signal /ADV is “L” (times T22 to T24).
Subsequently, at the time T23, the output enable signal /OE turns to “L”, and thereby, the memory starts the internal read operation, and releases the Hi-Z state of the output to be the Low-Z state. At the time T24, the address valid signal /ADV turns to “H”. At the time T25 when a predetermined time elapses from the time T23 when the internal read operation is started, the memory outputs the data (DATA) read by the internal read operation from the shared pad of address/data (ADQ) to external.
As stated above, in the operation example shown in FIG. 8, the external address is inputted to the memory at the times T22 to T24, but after the time T23, the output of the memory becomes the Low-Z state by releasing the Hi-Z state thereof. Accordingly, the bus fight occurs during the period from the time T23 to the time T24. Besides, the bus fight may similarly occur when the address valid signal /ADV and the external address inputted to the memory delay caused by a load of a signal line.
Consequently, in the conventional memory, a margin must be provided in an interval from the end of the external address input to the start of the internal read operation, and the start of the internal read operation must be delayed.